The art disclosed in the specification of Japanese Patent Kokai Publication JP-A-8-320835 is an example of the related prior art. Specifically, FIG. 7 illustrates a system of checking information relating to the connections of a 3-stage switch having a switch size of M.times.N in which M incoming lines and N outgoing lines are selectively connected, where M and N represent natural numbers.
As shown in FIG. 7, the switch section of this 3-stage switch includes P discrete switches 11, . . . , 1K, . . . , 1P (where P=M/m) of switch size m.times.r each selectively connecting m incoming lines and r outgoing lines (where m, r are natural numbers and m.ltoreq.M holds) and belonging to a primary switch group 1; R discrete switches 21, . . . , 2A, . . . , 2R each selectively connecting p incoming lines and q outgoing lines and belonging to a secondary switch group 2; Q discrete switches 31, . . . , 3K, . . . , 3Q (where Q=N/n) each selectively connecting r incoming lines and n outgoing lines and belonging to a tertiary switch group 3; and a main controller 4 for controlling connections through the primary, secondary and tertiary switches 1, 2 and 3, respectively.
The controller 4 has a memory 41 for storing information relating to the connections of each discrete switch.
The discrete switches belonging to each discrete switch group have a switch unit for connecting one of a plurality of input terminals and one of a plurality of output terminals, and a switch controller for connecting this switch unit with the memory 41.
By way of example, as shown in FIG. 8, a primary switch 1K which belongs to the primary switch group 1 incorporates a switch unit 1K1 and a switch controller 1K2.
Similarly, secondary switches 2A, 2B which belong to the secondary switch group 2 have switch units 2A1, 2B1, respectively, and switch controllers 2A2, 2B2, respectively. Likewise, tertiary switches 3H, 3K which belong to the tertiary switch group 3 have switch units 3H1, 3K1, respectively, and switch controllers 3H2, 3K2, respectively.
The switch controller 1K2 of the primary switch 1K is connected to the main controller 4 by a control line 62. The switch controllers of the other discrete switches are connected to he main controller by control lines in a similar manner.
The manner in which input and output terminals of each discrete switch are connected will be described with reference to FIG. 9.
An ath (1.ltoreq.a.ltoreq.r) output terminal 1Kao of the Kth (1.ltoreq.K .ltoreq.P) switch 1K of primary switch group 1 is connected to a kth (1.ltoreq.k.ltoreq.p) input terminal 2Aki of the Ath (1.ltoreq.A.ltoreq.R) switch 2A of secondary switch group 2 by a signal line 51. An hth (1.ltoreq.h.ltoreq.q) output terminal 2Aho of this switch 2A is connected to an ath (1.ltoreq.a.ltoreq.r) input terminal 3Hai of the Hth (1.ltoreq.H.ltoreq.Q) switch 3H of tertiary switch group 3 by a signal line 53. Further, a kth (1.ltoreq.k .ltoreq.p) output terminal 2Ako of the switch 2A is connected to an ath input terminal 3Kai of the Kth (1.ltoreq.K.ltoreq.Q) switch 3K of tertiary switch group 3 by a signal line 54.
Further, a bth (1.ltoreq.b .ltoreq.r) output terminal 1Kbo of the switch 1K is connected to a kth input terminal 2Bki of the Bth (1.ltoreq.B.ltoreq.R) switch 2B of secondary switch group 2 by a signal line 52.
Further, an hth output terminal 2Bho of the Bth switch 2B of secondary group 2 is connected to a bth input terminal 3Hbi of the switch 3H by a signal line 55, and a kth output terminal 2Bko of the switch 2B is connected to a bth input terminal 3Kbi of the switch 3K by a signal line 56.
Accordingly, in the arrangement illustrated in FIG. 7, the output terminals 1.about.r of the first switch 11 in primary switch group 1 are connected to the first input terminals (1) of the 1st.about.rth switches 21.about.2R, respectively, of secondary switch group 2.
Similarly, the output terminals 1.about.q of the first switch 21 in secondary switch group 2 are connected to the first input terminals (1) of the switches 31.about.3Q, respectively, of tertiary switch group 3.
Thus, the output terminals of each discrete switch are cross-connected to the input terminals of the switches of the next stage.
A method of connecting paths in a 3-stage switch having such a construction will now be described with reference to FIG. 9.
In a case where there is a request to connect an input terminal X (where X.ltoreq.M) of the overall 3-stage switch and an output terminal Y (where Y.ltoreq.N), the main controller 4 computes that the input terminal X corresponds to an input terminal .alpha. of the Kth switch 1K of primary switch group 1 and that the output terminal Y corresponds to an output terminal .beta. of the Hth switch 3H of tertiary switch group 3. By using the memory 41, the status of use of output terminal .beta. of switch 3H is detected and the following processing is executed based upon the results of detection:
(1) In a case where the output terminal .beta. of switch 3H is currently in use, an input terminal of the 3-stage switch that will make the connection to .beta. (or Y) is retrieved. If the retrieved input terminal is X, the status is made "already connected" because the path for which connection was requested has already been connected. If the retrieved input terminal is different from X, then the status is made "connection impossible".
(2) In a case where the output terminal .beta. of switch 3H is not in use, the main controller 4 retrieves from the memory 41 the states of use of output terminals 1.about.r of switch 1K of primary switch group 1 successively starting from the first output terminal.
For example, if 1st.about.(a-1)th output terminals of switch 1K are in use and the ath output terminal 1Kao is not use, the main controller 4 next retrieves the status of use of output terminal 2Aho of switch 2A of secondary switch group 2 connected to switch 3H of tertiary switch group 3 to which output terminal .beta. belongs.
If this output terminal 2Aho is not in use, a path connecting the input terminal X and output terminal Y of the 3-stage switch can be acquired by connecting input terminal 1K.alpha.i and output terminal 1Kao of switch 1K of primary switch group 1, input terminal 2Aki and output terminal 2Aao of switch 2A of second switch group 2, and input terminal 3Hai and output terminal 3H.beta.o of switch 3H of tertiary switch group 3. Accordingly, instructions for connecting the input and output terminals of the discrete switches along the retrieved path are transmitted to the switch controllers of the discrete switches.
In a case where each discrete switch executes the connection of the requested path to connect the input and output terminals normally, the status "normal end" is sent back to the main controller 4.
In a case where the path has been connected as requested, the main controller 4 saves the connection information (the switch numbers of the discrete switches, the input terminal numbers and the output terminal numbers of the discrete switches), which has been set for each of the discrete switches, in the memory 41.
In a case where the output terminal 2Aho of switch 2A is in use, on the other hand, the main controller 4 retrieves the status of use of the bth (a&lt;b) output terminal 1Kbo of switch 1K. If this output terminal is not in use, the main controller next retrieves the status of use of the hth output terminal 2Bho of switch 2B connected to switch 3H. The main controller 4 repeats the operation described above until a usable output terminal of a primary switch and output terminal of a secondary switch are found.
A method of checking the connection information of such a multistage switch according to the prior art is as follows: Before generating a required connection instruction for each discrete switch, a check is made in regard to the discrete switch connection information that has been stored in the memory 41. Specifically, the fact that the discrete switches constructing the multiple stages are permanently connected in accordance with a prescribed rule is utilized to check, for each connection path, whether the output terminal number of a switch of a cth (c.ltoreq.S-1) stage of the multistage switch and the input terminal number of a switch of the (c+1)th stage are capable of being logically connected, and to check whether the input terminal number and output terminal number of each discrete switch that have been stored in the memory unit as well as the switch number in the multistage switch fall within appropriate limits, thereby checking the logical normality of the multistage switch connection information that has been stored in the memory.
If the result of the logical check of the connection information is "normal", then, in regard to a path X-Y for which connection has been requested anew, the main controller 4 retrieves output terminals, which are not in use, based upon the connection information in memory 41 and generates a connection instruction each discrete switch is required to execute. Consequently, the logical validity of the connection information is assured. Furthermore, in a case where the result of the connection from the switch controller of each discrete switch is indicative of "normal end", the main controller 41 verifies that the path for which connection is requested has been set reliably for each discrete switch and adds the information indicative of the input and output terminals for which the path has been set onto the connection information in the memory 41.